This invention relates generally to fabrication of capacitors in a DRAM cell and, more particularly, to a method and process for fabricating stacked-capacitors with a large capacitance.
A DRAM cell is in general a semiconductor memory device with one transistor and one capacitor, in which data of 1-bit can be stored in the capacitor by the charge stored therein. As a tendency to higher density of an integrated semiconductor device causes the density of the DRAM cells to be increased, the area occupied by one memory cell becomes gradually decreased. Therefore, the present invention is devoted to the manufacture of a capacitor with a maximum capacity in a limited area.
FIGS. 1A-1C represent known fabrication processes of a stacked-capacitor according to the conventional method. In FIG. 1A, a field oxide layer 12 for the separation of respective cells is formed in a portion of a substrate 10 of a first conductivity. Then, in order to prepare a source region 18, a layer of second conductivity is formed by an ion injection near the field oxide layer 12. A drain region 20 separately distanced from the field oxide layer 12 is formed. A first oxide layer 22 covers the entire surface of the substrate 10 except some parts of the source region 18. Between the source and drain regions 18, 20, a gate electrode 16 is formed thereon, while a gate oxide layer 14 is provided as an intermediate layer. Thereafter, a source contact region 23 is formed by etching the first oxide layer 22 on the source region 18, in a manner of a conventional etching process.
In FIG. 1B, after formation of a first polycrystalline silicon layer over the source region 18, a storage electrode 24 is formed by etching the predetermined region of the first polycrystalline layer.
In FIG. 1C, the stacked-capacitor having a typical stacked structure is completely fabricated by forming a plate electrode 28 along the top surface of a dielectric layer 26 by etching a predetermined region after spreading the dielectric layer 26 on the surface of the storage electrode 24 and by forming a second polycrystalline silicon layer over the entire surface of the substrate 10. In a conventional stacked-capacitor as shown in FIG. 1C, when the area occupied by a cell is reduced, the areas occupied by the storage electrode 24 and the plate electrode 28 are also reduced. Therefore, there is a problem in that the sufficient capacity required in a high density semiconductor memory device of more than 64 Mega bits cannot be secured. Therefore, as a way of increasing the capacity of the capacitors, the cylindrically structured stacked-capacitor is proposed.
FIGS. 2A-2F show the fabrication method of the cylindrical structure stacked-capacitor by using an alternative method.
In the drawings, in order to separate the cells, the field oxide layer 42 is formed on one end of the substrate 40 of a first conductivity. An ion-injection of a second conductivity is made so as to prepare a source region 48 in contact with the field oxide layer 42. Separately distanced from the source region 48, a drain region 50 is formed. A first oxide layer is formed over the entire surface of the substrate 40 on which a gate electrode 46 is formed making a gate oxide layer 44 for an intermediate layer, the gate oxide layer 44 being positioned on and between the source and drain regions 48, 50, and thereafter a source contact region 53 is formed by etching the first oxide layer on the top surface of the source region 48. In this case, the first insulation layer 52 is the HTO (high temperature oxide) layer with a thickness of more than 9,000 .ANG..
The nitride layer 54 with a thickness of 1,500 .ANG. is then deposited using the conventional LPCVD (low pressure chemical vapor deposition) technique on the surface of the first insulation layer 52, as shown in FIG. 2B. Then, the side walls 54a of the nitride layer are formed on both sides of the first insulation layer 52 by using dried-etching, as shown in FIG. 2C. In FIG. 2D, as a result of the so-called Etch-Back in either dried-etching or damped-etching technique, the first insulation layer 52a etched in the above method is deposited in an approximate thickness of 3,000 .ANG.. Then, the cylindrical structured capacitor is completely made by forming sequentially the first polycrystalline silicon layer 56 in contact with the source region 48, dielectric compound layer 58 made of both the oxide layer and the nitride layer, and the second polycrystalline silicon layer 60.
The first and second polycrystalline silicon layers 56, 60 are deposited by using the conventional LPCVD technique, and the thickness of the dielectric 58 is between 50 to 60 .ANG.. A problem associated with this is that the fabrication process may be difficult, even though the capacity of the capacitor is increased more than the conventional stacked-capacitor.
Furthermore, as the difference between the cylindrical side walls 54a of the nitride layer is so wide, the subsequent process can be troublesome because of the bad step coverage.
On the other hand, in the conventional stacked-capacitor, the thickness of the storage electrode is limited to a certain thickness because of the limitation of the photographic technique. That is, there was a problem in that the bathtub-shaped capacitor required a more delicate pattern than that of the lower part polycrystalline silicon, because the limited photographic technique is applied during the formation of the underlying polycrystalline silicon layer in case of the manufacture of 64 Mega-bit DRAM.